A Low Power 10-bit Pipelined ADC Using Capacitance Coupling Technique

This paper presents 10-bit, 1.5 MS/s, 2.5V, Low Power Pipeline analog to digital converter using capacitor coupling techniques. A capacitance coupling foldedcascode amplifier effectively saves the power consumption of gain stages of ADC in a 0.25 μm CMOS technology. The ADC also achieves Low power Consumption by the sharing an op-amp between two successive pipeline stage further reduction of power is achieved by removing front end SH circuit from third stage onwards. The ADC, implemented in a 0.25 μm CMOS technology, achieves 10-bit resolution and consumes 13.3 mW power at 5 MHz sampling frequency. Index term Analog to Digital conversion, capacitor sharing, high speed opamp-sharing pipelined analog to digital convertor, Low power .